The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V is designed for space applications: with its high-performance and fault-tolerant design, NOEL-V is the ideal choice for satellites, rovers, and other space-bound systems. Built on the RISC-V architecture, NOEL-V offers unparalleled flexibility and customization, allowing SoC designers to create solutions tailored to their specific needs. Software developers have access to a vast library of existing software and tools to help them create the perfect solution.

The processor is the first released model in our RISC-V line of processors that complement the LEON line of processors.

Architecture

The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel. To support the instruction issue rate of the pipeline, the NOEL-V has advanced branch prediction capabilities. The cache controller of the NOEL-V supports a store buffer FIFO with one cycle per store sustained throughput, and wide AHB slave support to enable fast stores and fast cache refill.

The NOEL-V is interfaced using the AMBA 2.0 AHB bus (but a subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file.
Check out the detailed feature set!

Availability and licensing

NOEL-V is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here.

The NOEL-V can also be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use NOEL-V in a commercial product.

Evaluation bitfiles

We also provide NOEL-V example bitfiles for evaluation purposes. FPGA programming files are available for the following FPGA boards:

- Digilent Arty-A7: NOEL-ARTYA7 example designs

- Microsemi PolarFire Splash Kit: NOEL-PF example designs

- Xilinx KCU105: NOEL-XCKU example designs

Software ecosystem

The NOEL-V processor implements the RISC-V ISA which means that compilers and kernels for RISC-V can be used with NOEL-V (kernels will need a NOEL-V BSP). To simplify software development, we provide several prebuilt toolchains. Currently, the NOEL-V processor is supported by pre-built RTEMS and Linux toolchains. We provide VxWorks 7 BSP for NOEL-V under a commercial license. Over time, the NOEL-V software support will be extended to the same level of support that exists for the LEON line of processors.

The GRMON debug monitor interfaces to the NOEL-V on-chip debug support unit, implementing a large range of debug functions including GDB support for source level debugging.

Visit the NOEL-V Software ecosystem webpage for all the details.

Synthesis

The NOEL-V processor is inherently portable and can be implemented on any FPGA and ASIC technologies. 

For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs

Estimation of the resource utilization for the NOEL-V can be found here:

Excel sheet for SoC area estimation

Fault Tolerance

The cache memories of the NOEL-V processor are safeguarded from radiation-induced Single Event Upsets (SEUs) through a patent-protected error correction scheme. This scheme is capable of correcting single bit errors, detecting double bit errors, and even detecting 3-bit and 4-bit adjacent bit errors. The correction is implemented transparently in the cache controller without the need for software intervention or extra memory access.
Additionally, the caches include a hardware mechanism that can be activated to automatically scrub the memories, preventing error accumulation. The fault tolerance features can be activated in all the NOEL-V configurations.

Quick Links

- Documentation

- Development roadmap

- Detailed feature set

- Software Ecosystem

- Download open-source code (GPL license)

- Excel sheet for SOC area estimation

- DISCOURSE community (for open-source users)

NOEL-V configurations

The NOEL-V processor core is available as part of a subsystem that also contains system peripherals. The subsystem can be configured to use the processor configurations listed in the table below. The configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is also possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem

 Key for RISC-V extensions column:

• RV32I - 32-bit Base Integer instructions
• RV64I - 64-bit Base Integer instructions
• M - Hardware support for multiply and division
• A - Atomics
• FD - Single/Double Floating Point
• G - short for IMAFD
• C - Compressed instructions
• H - Hardware hypervisor support
• B - Bit manipulation instructions

Configuration

Required license

Target

Architecture

Pipeline

RISC-V extensions

MMU

PMP

Privilege modes

Example SW

HP

General

High-performance processing

32 or 64 bits

Dual issue

IMAFDB*CH

Yes

Yes

Supervisor, User and Machine + Virtualization

Hypervisor, Linux, VxWorks

GP

General (dual-issue pipeline)
Entry (single-issue pipeline)

General purpose processing

32 or 64 bits

Dual or single issue

IMAFDB*CH

Yes

Yes

Supervisor, User and Machine + Virtualization

Hypervisor, Linux, VxWorks

GP-lite

General (dual-issue pipeline)
Entry (single-issue pipeline)

General purpose processing      Area optimized

32 or 64 bits

Dual or single issue

IMAFDB*C

Yes

No

Supervisor, User and Machine

Linux, VxWorks

MC

Entry

Controller applications

32 or 64 bits

Single issue

IMAFDB*C

No

Yes

User and Machine

RTEMS

MC-lite

Entry

Controller applications    Area Optimized

32 or 64 bits

Single issue

IMA

No

No

User and Machine

RTEMS

Detailed Feature set

The NOEL-V processor can implement the following features:

• RISC-V 32-bit and 64-bit architecture
• Hardware multiply and divide units
• Compressed (16 bit) instruction support
• Atomic instruction extension
• 32/64 bit floating point extensions using non-pipelined area efficient FPU or high-performance fully pipelined IEEE-754 FPU
• Machine, supervisor and user mode. RISC-V standard MMU with configurable TLB
• RISC-V Hypervisor (H) extension (adding virtual supervisor mode and virtual user mode)
• Fault Tolerance
• Robust and fully synchronous single-edge clock design
• Large range of software tools: compilers, kernels and debug monitors
• High Performance*: CoreMark: 4.03** / 4.69*** CoreMark/MHz
  ^{*For HPP64 configuration. CoreMark score varies with processor configuration, microarchitectural changes, and toolchains. The CoreMark score is preliminary and will be updated for the v4 and v5 milestones.
  **-march=rv64im -mabi=lp64 -O2 -funroll-all-loops -funswitch-loops -fgcse-after-reload -fpredictive-commoning -mtune=sifive-7-series
  -finline-functions -fipa-cp-clone -falign-functions=8 -falign-loops=8 -falign-jumps=8 --param max-inline-insns-auto=20 using GCC 9.2.0 under RTEMS 5
  *** Using "#define ee_u32 int32_t" in core_portme.h, as is common for 64 bit RISC-V.}

• RISC-V standard APLIC
• RISC-V standard PMP (physical memory protection)
• RISC-V standard external debug support
• RISC-V watchdog
• RISC-V IOMMU
• Support for RISC-V bit manipulation extensions: Zba/b/c/s, Zbkb/c/x
• Support for counter interrupt RISC-V extensions: Sscofpmf
• Support for cache management operations RISC-V extension: Zicbom
• Support for Sstc RISC-V extension
• Advanced dual-issue in-order pipeline
• Dynamic branch prediction, branch target buffer and return address stack
• Four full ALUs, two of them late in the pipeline to reduce stalls
• Separate instruction and data L1 cache (Harvard architecture) with snooping
• Optional L2 cache: 256-bit internal, 1-4 ways, 16 KiB - 8 MiB
• Native AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide
  • Subsystem including processor and Level-2 cache with AXI4 backend also available.

GRLIB IP Core User's Manual,  see NOELVSYS

NOEL-V Product Brief.pdf (March 2023)

• New AIA interrupt controller APLIC and IMSIC
• New ACLINT to replace CLINT
• RISC-V watchdog
• Debug module improvements

Features in the roadmap for release include:

• Support for standardized co-processor interface
  
• Support for CFI (Control Flow Integrity) checks
• Multi-lane bus interface (L1 and L2)
• Smepmp extension support
• V extension support
• Support for more resource-efficient floating-point implementations (single- and half-precision floating-point unit)