LEON5

The processor pipeline design of the LEON5 is significantly enhanced compared to earlier LEON3 and LEON4 processors, and initial evaluations show that LEON5 can provide up to 85% faster execution for single-threaded integer benchmarks compared to LEON4. The main new feature of the LEON5 pipeline is the dual-issue functionality, allowing up to two instructions per cycle to be executed in parallel in the processor. To support the increased issue rate of the pipeline, the LEON5 has advanced branch prediction capabilities. The cache controller of the LEON5 supports a store buffer FIFO with one cycle per store sustained throughput, wide AHB slave support to enable fast stores and fast cache refill, as well as several other enhancements.

The LEON5  is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL and DIV instructions, an IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

The LEON5 processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for AMD/Xilinx FPGAs

Estimation of the resource utilization can be found here:

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Excel sheet for SoC area estimation

We also provide LEON5 example bitfiles for evaluation purposes, and FPGA programming files are available for the following FPGA boards:

• Microsemi PolarFire Splash Kit: LEON-PF example designs
• Xilinx KCU105: LEON-XCKU example designs

LEON5 is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here. The open source version of the LEON5 does not include features such as fault-tolerance and high-performance FPU.

The LEON5 can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON5 in a commercial product

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Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON5 (kernels will need a LEON BSP). To simplify software development, we provide several toolchains and operating systems. Check the software overview webpage for all the details.

LEON5 provides backward compatibility for software designed for LEON3 and LEON4 systems with the following exceptions:

• LEON5 does not support the SPARC V8e multiply-and-accumulate (MAC) instructions
• LEON5 does not support the LEON-REX instruction set
• Software that depend on version field values to identify LEON3 and LEON4 processors will see a different version value for LEON5

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The GRMON debug tool interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions.

The LEON5 processor will also be supported by our TSIM cycle-accurate simulator.

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Notes:
* Wide interface compatible also with 32-bit AHB masters and slaves

** L2 cache/IOMMU can be added externally as separate cores. These cores are licensed separately.

*** The higher performance GRFPU5 is recommended for configurations that need higher performance for floating-point calculations. GRFPU5 requires an additional license next to the Entry and General processor licenses.

The GRLIB IP library contains LEON5 template designs for several popular FPGA prototyping boards.

Pre-synthesized FPGA programming files are also provided, see LEON-XCKU and LEON-PF.

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