Status:
Available
GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.
GRCAN supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core. Separate transmit and receive buffers are assumed. Reception and transmission of sets of messages can be ongoing simultaneously.
The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:
Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation
The IP core is available as a separate package or as an part of commercial versions of the GRLIB VHDL library.
Contact sales@gaisler.com for licensing information
Device drivers for RTEMS and VxWorks are available for our CAN cores.
File
Category
Revision
Date
Access
Data sheet and user's manual
2024.2
2024-07-15
Free download
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