Ethernet 10/100

Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple ethernet packets can be received and transmitted without CPU involvement. The GRETH supports the MII and RMII PHY interfaces. Hardware support is also provided for the EDCL UDP debugging protocol. For critical space applications, a fault-tolerant version of GRETH is available with full SEU protection of all RAM blocks.

EDCL

The EDCL is an optional hardware unit providing read/write access to the AHB bus through ethernet using an UDP based protocol. It operates in parallel with the MAC DMA and does not interfere with the  normal network traffic other than lowering performance. Speeds up to 90 Mbit/s effective throughput have been achieved when accessing the AHB bus through the EDCL using the GRMON.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

The IP core is part of the GRLIB IP library, and as such provided in full source code under the GNU GPL License. Commercial licensing is also possible, contact sales@gaisler.com for more information.