I²C Slave

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

Specific support for Lattice FPGAs
Specific support for Microchip FPGAs
Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

Evaluation boards

Ordering information

Development Kit

Licensing

The IP core is part of the GRLIB IP library, and as such provided in full source code under the GNU GPL License.

Commercial licensing is also possible, contact sales@gaisler.com for more information

Software

Tools

Block diagram

Supported Hardware

Configuration

Reference Design

Other resources

Detailed features

AMBA APB interface
Optional programmable I²C address - The initial address is configurable via a VHDL generic. The designer can choose to leave the core's address programmable via an APB mapped register.
10-bit address support. If the core is configured without a hard coded address software may also configure the core to use 7-bit addressing.
Four main modes, core can be configured to force a master into wait mode by lowering the SCL line during reception and/or transmission. See GRIP manual for details.
Clock stretching

Downloads

File

Category

Revision

Date

Access

GRLIB IP Cores Manual

Data sheet and user's manual

2025.1

2025-03-28

Free download

Password/
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GRLIB User's Manual

Data sheet and user's manual

2025.1

2025-03-28

Free download

Password/
Contact us

Excel sheet for SoC area estimation

Data sheet and user's manual

2025.1

2025-03-28

Free download

Password/
Contact us

Overview

Architecture

Key Tech Spec

Target technology support

Evaluation boards

Ordering information

Development Kit

Licensing

Software

Tools

Block diagram

Supported Hardware

Configuration

Reference Design

Other resources

Detailed features

Downloads

Frequently asked questions