I²C to AHB Bridge

On the I²C bus the slave acts as an I²C memory device where accesses to the slave are translated to AMBA accesses. The core can translate I²C accesses to AMBA byte, halfword or word accesses. The core makes use of I²C clock stretching but can also be configured to use a special mode with clock stretching in order to support systems where limitations of the master or physical layer prevent stretching of the I²C clock period.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

The IP core is part of the GRLIB IP library, and as such provided in full source code under the GNU GPL License.

Commercial licensing is also possible, contact sales@gaisler.com for more information.