Reed-Solomon

The following Reed-Solomon codecs are available:

   RS(24, 16, 8, E=1) 16 bit data, 8 check bits, corrects 4-bit error in 1 nibble

   RS(40, 32, 8, E=1) 32 bit data, 8 check bits, corrects 4-bit error in 1 nibble

   RS(48, 32, 16, E=1+1) 32 bit data, 16 check bits, corrects 4-bit error in 2 nibbles (when located in separate halves)

   RS(48, 32, 16, E=2) 32 bit data, 16 check bits, corrects 4-bit error in 2 nibbles

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

• Specific support for Lattice FPGAs
• Specific support for Microchip FPGAs
• Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found here: Excel sheet for SoC area estimation

The IP can be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement.

Contact sales@gaisler.com for licensing information