SpaceWire CODEC

GRSPW_CODEC is the same codec as in the GRSPW2 but with a different host interface. Instead of using the advanced AMBA -AHB DMA and RMAP target a simple 9-bit wide FIFO interface is used instead. The host interface consists of 9-bit wide data interfaces to the FIFOs in both directions with accompanying read/write, full/character available and almost full/empty signals. The FIFOs can be configured from 16 to 2048 characters depth. Time-code transmission and reception is also supported using tickin/tickout and 8-bit timein/timeout signals.

The core properties and operation are controlled through a set of signals. They set the link speed during initialization and run-state, link interface FSM timeouts and control operations such as starting and disabling the link.

Compared to the GRSPW2, the CODEC core is useful in applications where the AMBA bus is not present, the source of data does not have an AMBA interface, low area is needed or when very detailed control of character transfer order and timing is needed.

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

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- Specific support for Lattice FPGAs
- Specific support for Microchip FPGAs
- Specific support for Xilinx FPGAs

Estimation of the resource utilization can be found in the download files below (Excel sheet for SoC area estimation).

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The IP core is available as a separate package or as an addition to commercial versions of the GRLIB VHDL library. Contact sales@gaisler.com for licensing information