The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.

 

Designs based on the GRLIB IP library are highly portable between target technologies and both target technology adaptions and template designs are available for Xilinx FPGAs. 

• GRLIB contains template designs for several FPGA boards (the set of included template designs changes with type of GRLIB distribution). A list of supported boards is available in the GRLIB IP Library User's Manual.
• GRLIB documentation and downloads are available via the GRLIB IP Library product page.
• The LEON line of processors are supported on Xilinx FPGAs. Evaluation bitstreams are available as part of the GRLIB bitstreams package and through:
• LEON-XCKU - LEON5 example designs for Xilinx Kintex Ultrascale FPGAs
• NOEL-XCKU - NOEL-V example designs for Xilinx Kintex Ultrascale FPGAs
• NOEL-ARTYA7 - NOEL-V example designs for Xilinx 7-Series FPGAs (Digilent Arty-A7 board)
• LEON-V5QV - Information on implementation of LEON SoC designs on Virtex-5QV FPGAs
• The GRSCRUB FPGA Supervisor IP core supports programming and scrubbing of Virtex-5 and Kintex Ultrascale FPGAs.