The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs.

LEON5 provides backward compatibility for most software implementations that have targeted LEON3 and LEON4 processors. The LEON5 primarily targets high-end FPGA:s and deep-submicron ASIC technologies. For legacy and less performant technologies, the LEON3 processor is the recommended choice that continues to be maintained.

Quick Links

- Documentation

- Development roadmap

- Detailed feature set

- DISCOURSE community (for open-source users)

- Software Ecosystem Overview

- Download open-source code (GPL license)

- Excel sheet for SOC area estimation

- GR765 - Octa-core LEON5FT SoC

Architecture

The processor pipeline design of the LEON5 is significantly enhanced compared to earlier LEON3 and LEON4 processors, and initial evaluations show that LEON5 can provide up to 85% faster execution for single-threaded integer benchmarks compared to LEON4. The main new feature of the LEON5 pipeline is the dual-issue functionality, allowing up to two instructions per cycle to be executed in parallel in the processor. To support the increased issue rate of the pipeline, the LEON5 has advanced branch prediction capabilities. The cache controller of the LEON5 supports a store buffer FIFO with one cycle per store sustained throughput, wide AHB slave support to enable fast stores and fast cache refill, as well as several other enhancements.

The LEON5 is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL and DIV instructions, an IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

Fault Tolerance

The cache memories of the LEON5 processor are safeguarded from radiation-induced Single Event Upsets (SEUs) through a patent-protected error correction scheme. This scheme is capable of correcting single bit errors, detecting double bit errors, and even detecting 3-bit and 4-bit adjacent bit errors. The correction is implemented transparently in the cache controller without the need for software intervention or extra memory access. Additionally, the caches include a hardware mechanism that can be activated to automatically scrub the memories, preventing error accumulation.

The processor core can also be implemented in a dual-core lock step or a triple modular redundancy configuration (TMR). In this case, selected sub-blocks are instantiated multiple times (dual or triple redundant) with comparison logic and voters at the sub-block boundary.  See the IP User's Manual for detailed information.

Availability and licensing

LEON5 is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here.

The LEON5  can also be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON5 in a commercial product.

Evaluation bitfiles

We also provide LEON5 example bitfiles for evaluation purposes. FPGA programming files are available for the following FPGA boards:

- Microsemi PolarFire Splash Kit: LEON-PF example designs

- Xilinx KCU105: LEON-XCKU example designs

Synthesis

The LEON5 processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software Ecosystem

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON5 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems.

Check the software overview webpage for all the details.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. The GRMON monitor interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions. The LEON5 processor will also be supported by our TSIM3 simulator.

Software compatibility

LEON5 provides backward compatibility for software designed for LEON3 and LEON4 systems with the following exceptions:

• LEON5 does not support the SPARC V8e multiply-and-accumulate (MAC) instructions
• LEON5 does not support the LEON-REX instruction set
• Software that depend on version field values to identify LEON3 and LEON4 processors will see a different version value for LEON5

When HW virtualization is implemented and enabled, these incompatibilities can be hidden by the hypervisor.

GRLIB IP Core User's Manual,  see LEON5SYS

LEON5 Product Brief.pdf (November 2021)

Detailed Feature Set

The LEON5 processor has the following features:

• SPARC V8 instruction set with V8e extensions and compare-and-swap
• Advanced dual-issue pipeline
• Complex dynamic branch predictor and small branch target buffer
• Addition of Late ALU to decrease pipeline stalls
• 64-bit single-clock load/store operation
• 64-bit 4-port register file
• Hardware multiply and divide units
• Hardware floating-point support
• Non-pipelined area efficient FPU (NanoFPU) or High-performance, fully pipelined IEEE-754 FPU including hardware support for denormalized numbers (GRFPU5)
• High performance:
• Dhrystone*: 3.23 DMIPS/MHz  (-O3, inlining allowed)
• Coremark* : 4.52 CoreMark/MHz (-O3,-funroll-all-loops -finline-functions -finline-limit=1000)
  * All the results generated using BCC 2.0.7 toolchain

• Separate instruction and data L1 cache (Harvard architecture) with snooping
• Optional L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
• SPARC Reference MMU (SRMMU) with TLB
• AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide

• Subsystem including processor and Level-2 cache with AXI4 backend also available
• Advanced on-chip debug support with instruction and data trace buffer, and performance counter
• Symmetric Multi-processor support (SMP)
• Power-down mode and clock gating
• Robust and fully synchronous single-edge clock design
• Large range of software tools: compilers, kernels, simulators and debug monitors

As with previous generation LEON processors, the LEON5 processor model is being continuously extended. Planned extensions include a more advanced version of LEON5 with virtualization features and higher-performance bus interconnect

v3

 LEON5FT, support for tightly coupled memory, and internal memory scrubber.

Available

v4

Release of LEON5 advanced subsystem (LEON5-ADV) with address-striped buses and IOMMU integration.

Planned

v5

LEON5 virtualization extensions

Planned

v6

LEON5 single-issue pipeline (LEON5-EP)

Planned