Section GRLIB

GRLIB IP Library

The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.

The library includes cores for AMBA AHB/APB control, the LEON3 - LEON5 SPARC processors, the NOEL-V RISC-V processor, 32-bit PC133 SDRAM controller, 32-bit PCI bridge with DMA, 10/100/1000 Mbit Ethernet MAC, 8/16/32-bit PROM and SRAM controller, 16/32/64-bit DDR/DDR2 controllers, USB 2.0 host and device controllers, CAN controller, TAP controller, SPI, I2C, UART with FIFO, modular timer unit, interrupt controller, and a 32-bit GPIO port. Memory and pad generators are available for Virage, Xilinx, UMC, Atmel, Altera, Actel, eASIC and Lattice.

The library is provided under the GNU GPL license, but can also be licensed under commercial licensing conditions. There are four main distributions of GRLIB: open source (GPL), commercial for FPGA and ASIC implementations (COM), fault-tolerant for programmable devices (FT-FPGA) and fault tolerant (FT) for ASIC implementations. The distributions differ in terms on included IP and supported target technologies. Please refer to the GRLIB IP Core User's Manual for a complete list of all IP cores together with information on in which GRLIB distribution(s) each IP core is included or available.

This email address is being protected from spambots. You need JavaScript enabled to view it. if you want to use GRLIB in a commercial product.

Documentation and downloads

GRLIB contains template designs for several FPGA boards (the set of included template designs changes with type of GRLIB distribution). A list of supported boards is available in the GRLIB IP Library User's Manual.

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