The NOEL-V processor and the GRLIB IP library has support for Xilinx Kintex Ultrascale devices. This support consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contains a template designs for developments boards such as the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit and infrastructure that automatically builds project files for Xilinx Vivado and synthesis tools such as Mentor Precision Hi-Rel and Synopsys Synplify Premier. More information about GRLIB and our IP cores is available on the SoC library page.


Example designs

We provide prebuilt bitstreams of the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit NOEL-V template design. These bitstreams are intended for evaluation of software running on a NOEL-V SoC. To evaluate these designs, the following items are required:

The example design range is called NOEL-XCKU-EX:

Software components for NOEL-XCKU: