GRSPWROUTER SpaceWire Routing Switch

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of FPGA and ASIC technologies. The core supports all mandatory and optional features in the ECSS-E-ST-50-12C standard and can be configured from the minimum number of ports 2 to the maximum 31. In addition to this there is the mandatory configuration port. The configuration port provides access to configuration and status registers and the routing table using the Remote Memory Access Protocol (RMAP) defined in ECSS-E-ST-50-52C. The SpaceWire Plug-and-Play (PnP) protocol can optionally be supported on the configuration port.

Features

  • Compliant with ECSS-E-ST-50-12C
  • Routing
    • Non-blocking switch-matrix connecting any input port to any output port
    • Path, Logical and Regional Logical addressing
    • Group Adaptive Routing (GAR): from 1 port to all ports for both path and logical addresses
    • Packet distribution: from 1 port to all ports for both path and logical addresses
    • Two priority levels for output port arbitration
  • Configuration port using the RMAP protocol  with optional support for the SpaceWire PnP protocol (currently SpaceWire-PnP Protocol Definition, Draft A Issue 2.1)
  • 2 - 31 ports individually configurable as SpaceWire, FIFO or AMBA ports
  • Supports high data rates. Up to 200 Mbit/s in both directions on a single link on Microchip RTAX and up to 400 Mbit/s on Xilinx Virtex 4
  • System-time distribution
  • Optional AMBA AHB slave interface for fast access to the configuration area and routing table
  • Technology independent design. Can easily be implemented on a wide range of ASIC and FPGA technologies
  • Easily expandable through the AMBA AHB bus to other bus types such as Mil-Std-1553B, CAN bus, Ethernet and USB
  • Optional timers on ports to prevent locking situations

The GRSPWROUTER supports the external UT200SpWPHY01 SpaceWire Physical Layer Transceiver

  
GRSPWROUTER block diagram

Benefits

The different port types along with the high degree of configurability and technology support makes the core very suitable in a wide range of different systems and makes it possible for designers to optimize area and performance. It can be made as a standalone router ASIC, FPGA or as part of an AMBA bus based processor system. In each case the router core and configuration space will be the same making it easy to migrate to new systems. The core provides numerous interfacing possibilities. 

A wide range of configuration registers and signals are provided, allowing the user to have full control of the router, for example to disable configuration accesses from certain ports or to filter time-code propagation.
     
 

Area and timing

Estimation of the resource utilization for the GRSPWROUTER can be found here:

Excel sheet for SoC area estimation

Availability

The router IP is integrated within the GR718B SpaceWire router and can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages:

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs

Documentation

The GRSPWROUTER documentation can be found in GRLIB User's Manual