The second edition of the GR740 User Day was collocated with the RISC-V In Space Workshop. Access the event.
Are you curious about starting a new engaging role, at a world-leading company that works towards European Space Agency and NASA? Then this is your opportunity. We are continuously looking for experienced hardware and software engineers. We welcome your application!
Access our career page or contact us through career (at) gaisler.com.
Ever wonder which microprocessor to use in your space system design?
Check out this white paper which discusses the differences between LEON/SPARC and NOEL-V/RISC-V architectures. The paper describes our past and ongoing component development and explains the rationale for some architectural design choices for future roadmap products. Included herein are trends in the Space industry that are driving key new features example application use-cases and tradeoffs from a software perspective of a legacy LEON/SPARC design vs. a new RISC-V architecture.
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The NOEL-V is a synthesizable VHDL model of a processor that implements the open RISC-V architecture from the RISC-V International organization.
This is the first released model in the RISC-V product line of processors. Seven different configurations are now available for NOEL-V, ranging from a tiny 32-bit version to a 64-bit high performance version. NOEL-V complements the LEON line of processors. Click here for more information.
Dual-Core LEON3-FTGR712RC Radiation-hard Dual-Core LEON3-FT Processor, 200 MIPS, 200 MFLOPS |
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Quad-Core LEON4-FTGR740 Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS, QML-V/QML-Q |
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![]() GR740 CG625 |
The GR740 component has received QML-V and QML-Q quality certification by DLA in Q2 2022. Access the GR740 SMD 5962-21204.
Quad-Core LEON4-FTGR740-PBGA Plastic Radiation-hard Quad-Core LEON4-FT Processor, 1000 MIPS, 1000 MFLOPS |
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NOEL-V processor model LEON5 processor model GRLIB IP Library 2023.1-b4282 GR712RC user's manual 2.15 GR712RC data sheet 2.4 GR740 user's manual 2.5 GR716A data sheet 3.2 GR718B user's manual 3.8 |
GRMON3 Debug Monitor 3.3.3 GRMON2 Debug Monitor 2.0.99 TSIM3 LEON Simulator 3.1.9 TSIM2 LEON/ERC32 Simulator 2.0.66 BCC Bare-C Compiler 2.2.3 RCC RTEMS Compiler 1.2.25, 1.3.1 VxWorks 7 support for LEON VxWorks 6.9 support for LEON |
LEON/GRLIB examples for Lattice Certus/Pro-NX-RT |
We are proud to be a Gold Sponsor of the RISC-V Summit Europe, organized by RISC-V International. Meet us at booth #24 and talk with some of the developers of the NOEL-V, our RISC-V processor implementation.
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This year we are sponsoring the DASIA conference, organized by ASD-EUROSPACE in Sitges, Spain. Please visit our booth and don't miss the presentations on our rad-hard mixed-signal GR716A/B LEON3FT microcontroller, and the GR765, a cutting-edge SPARC and RISC-V octa-core microprocessor that will revolutionize space computing.
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Space applications pose significant challenges for electronic systems as they must contend with a myriad of environmental factors once they have been launched. To tackle these challenges, advanced processors specifically designed for space applications have become crucial. Read this blog post to learn more about the NOEL-V processor, a cutting-edge processor core that has been tailored for space missions. The NOEL-V implements the RISC-V International instruction set architecture (ISA) and can be found in our future rad-hard components.
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We are delighted to announces that our designs and products will be used in the upcoming JUpiter ICy moons Explorer (JUICE) mission. The mission, led by the European Space Agency (ESA), will investigate the largest planet in our solar system, Jupiter, and its icy moons, in search of possible habitable environments and signs of life. Seven out of the ten JUICE science instruments use the GR712RC.
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Meet us during the Space Symposium, arranged is by the Space Foundation on April 17-20 in Colorado Springs, US. You can find us in the North Hall where we are sharing booth #1042 with our former colleagues from CAES.
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We are presenting the "Development of the Fifth Generation European Processor for Space Applications: RISC-V Expanding in the Solar System" paper at the Gothenburg RISC-V Meetup taking place on 29 March 2023 in Gothenburg, Sweden.
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We are sponsoring and presenting the "GR765: The Next Generation LEON5 and RISC-V Fault Tolerant Processor" paper at the Spacecraft Flight Software Workshop (SFW2023) that will take place on March 20 - 23 2023 in Pasadena, CA. The Jet Propulsion Laboratory in conjunction with the Johns Hopkins University Applied Physics Laboratory, the Aerospace Corporation, NASA Goddard Space Flight Center and Southwest Research Institute, is hosting the 16th annual workshop at the California Institute of Technology.
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We are presenting and exhibiting at the SpacE FPGA Users Workshop (SEFUW 2023) that will take place on March 14 - 16 2023 at ESTEC in Noordwijk, The Netherlands. We will be presenting and demonstrating our fault-tolerant GRLIB IP core library and the LEON3FT/LEON4FT/LEON5FT and NOEL-V processor cores that support all FPGA types on the market suitable for space flight.
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We are exhibiting at Embedded World 2023 exhibition and conference that will take place on March 14 - 16 2023 in Nuremberg, Germany. Meet us in booth 2-550 in Hall 2.
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In 2019, we arranged the CAN in Space workshop here in Gothenburg together with the European Space Agency - ESA. We have now also participate in the CiA Workshop: CAN in satellites, sharing our broad portfolio of CAN based products for space. The 2-hour workshop took place on March 8, 2023. We are happy to see that the CAN in Automation (CiA) organization is continuously supporting the use of CAN in space and arranging this workshop dedicated to space.
We are presenting the "GR765 & GR7xV rad-hard RISC-V multi-core processors" paper at the European Space Components Conference ESCCON 2023 that will take place on March 7 - 9 2023 in Toulouse, France.
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We are exhibiting and presenting at the Swedish Space Forum (Rymdforum) in Kiruna on 5-7 March 2023.
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We are presenting the "CSSTII – Certifiable System-On-Chip for Safety Critical Industrial Applications" paper at the Swedish Cyber Security Collaboration Conference on 26th of January 2023. The presented work is based on our NOEL-V processor implements the RISC-V International instruction set architecture.
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We are pleased to announce a new strategic partnership to support space missions. IAR Systems is set to release a new version of the IAR Embedded Workbench for RISC-V that will support the NOEL-V, a fault-tolerant RISC-V compliant processor core from Gaisler. The partnership is another example of progress toward global adoption of RISC-V in space missions.
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GR740 quad-core LEON4FT SPARC V8 Microprocessor has been launched onboard the Rashid Rover on December 11 and is now heading to the moon. The Rashid Rover was developed by the Mohammed Bin Rashid Space Center and is traveling to the moon onboard the Mission 1 lunar lander as part of the HAKUTO-R lunar exploration program.
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We are pleased to announce that we have won a commercial license for our RISC-V/NOEL-V processor IP core with Idaho Scientific, based in Boise, Idaho. Idaho Scientific specializes in solutions that prevent hardware and software security attacks. These solutions help protect high-reliability systems that support critical infrastructure.
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