The core provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave. The SPI bus parameters are highly configurable via registers, the core has configurable ord length, bit ordering and clock gap insertion. All SPI modes are supported and also a 3-wire mode where the core uses one bidirectional data line. In slave mode the core synchronizes the incoming clock and can operate in systems where other SPI devices are driven by asynchronous clocks. The core can also be configured to automatically perform periodic transfers of a specified length.

Features

• AMBA APB interface
• Both master and slave operation
• Software programmable clock frequency
• Configurable FIFO depth
• Supports all SPI modes
• Configurable word length (4 - 32 bits, but the core supports back-to-back transactions and thereby allows longer words)
• Configurable bit ordering
• Clock gap insertion

For more information, please see the GRLIB IP Core User's Manual

Drivers

• We provide initialization code and drivers for RTEMS and Linux 2.6+.

Availability

• The core is available under a commercial license and also under the GPL.