GRSPW2 SpaceWire Link

The GRSPW2 core implements a SpaceWire link controller with RMAP support and AMBA host interface. The core complies to the SpaceWire standard (ECSS-E-ST-50-12C) with the protocol identification extension (ECSS-E-ST-50-51C) and RMAP protocol (ECSS-E-ST-50-52C). Receive and transmit data is autonomously transferred between the SpaceWire Codec and the AMBA AHB bus using DMA transfers. Through the use of receive and transmit descriptors, multiple SpaceWire packets can be received and transmitted without CPU involvement. The GRSPW2 control registers are accessed through an APB interface. For critical space applications, a fault-tolerant (FT) version of GRSPW2 is available with full SEU protection of all RAM blocks.

GRSPW2 User's Manual

GRSPW2 Product Sheet

GRSPW block diagram

New features

GRSPW2 is the successor to the GRSPW. It is based on the old core and contains all of its functionality and features while also adding new ones. The major differences are shown in the table below.

Feature	GRSPW	GRSPW2
RMAP	Draft C	Draft F
Clock factor	4	8
DMA channels	1	4
Timers	System clock	SpaceWire clock
Addressing	Single address	Multiple addresses and ranges

GRPSW2 implements RMAP error code 12 (Invalid destination logical address) which is the only part missing in GRSPW (not making it draft F compliant).
The clock factor is the largest difference in clock frequency between the AHB clock and the SpaceWire clock. GRSPW2 has doubled this factor.
Up to four DMA channels can be implemented in GRSPW2 while the old core only supports one.
The GRSPW required configuration of the disconnect and 6.4 us timers since they used the system clock. The new core uses the SpaceWire transmit clock which makes that extra configuration step unnecessary.
GRSPW2 supports separate logical addresses for each DMA channel with a corresponding mask that can be used to disable individual bits during address comparison effectively creating address ranges.

Area and timing

Estimation of the resource utilization for the GRSPW2 can be found here:

Excel sheet for SoC area estimation

Features

Full implementation of SpacewWire standard
Protocol ID extension ECSS-E-50-11
Optional RMAP protocol ECSS-E-50-11
AMBA AHB back-end with DMA
Descriptor-based autonomous multi-packet transfer
Low area and high frequency
SEU protection fault-tolerance
Portable

Benefits

Tested and verified against several other SpaceWire cores
Low area and high frequency
Easily portable between FPGA and ASIC
Low-cost project license
SEU protection of all RAM blocks

Deliverables

FPGA/ASIC netlist
Stand-alone testbench
Optional plug and play interface for GRLIB IP library
User's manual
Driver for RTEMS and VxWorks

Availability

The IP can be implemented in any ASIC or FPGA technology. For specific information related to Xilinx, Microchip, and Lattice FPGAs, please refer to our dedicated web pages: