Section GRLIB

Section GRLIB



The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.

The library includes cores for AMBA AHB/APB control, the LEON3 - LEON5 SPARC processors, the NOEL-V RISC-V processor, 32-bit PC133 SDRAM controller, 32-bit PCI bridge with DMA, 10/100/1000 Mbit Ethernet MAC, 8/16/32-bit PROM and SRAM controller, DDR/DDR2/DDR3 controllers, USB 2.0 host and device controllers, CAN controller, TAP controller, SPI, I2C, UART with FIFO, modular timer unit, interrupt controller, and a 32-bit GPIO port. Memory and pad generators are available for Virage, Xilinx, UMC, Atmel, Altera, Microchip, NanoXplore, eASIC and Lattice.

GRLIB contains template designs for several FPGA boards. A list of supported boards is available in the GRLIB IP Library User's Manual.










The open-source version of the library is distributed under the GNU GPL license and can be downloaded here.

GRLIB can also be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. The commercial distributions differ in terms of included IP and supported target technologies. Please refer to the GRLIB IP Core User's Manual for a complete list of all IP cores together with information about which GRLIB distribution(s) include each IP core.

Contact us if you want to use GRLIB in a commercial product.



 GRLIB Community

The open-source users of the library can benefit from GRLIB
, a discussion platform that can be used to seek help, share information, discuss and collaborate.


Documentation and downloads

- GRLIB User's Manual

- GRLIB IP Core User's Manual

- Download GRLIB VHDL source code

- Excel sheet for SOC area estimation

- Specific support for Lattice FPGAs

- Specific support for Microchip FPGAs

- Specific support for Xilinx FPGAs


Template Designs and evaluation bitstreams

GRLIB supports many different ASIC and FPGA technologies. To easily get started with your design, GRLIB provides templates for many different FPGA evaluation boards. In this way, you can find examples on how to instantiate GRLIB IPs in your target technology and also start your development from a solid base. 

A list of the supported FPGA evaluation boards is available in the GRLIB IP Library User's Manual.

We also provide evaluation bitstreams for our processors.
See LEON examples and NOEL-V examples


The GNU GPL license

GPL (GNU General Public License) is a widely-used free software license that guarantees end users the freedom to run, study, and modify the software. The GPL requires that any derivative works must also be licensed under the same terms, ensuring that any changes to the original software also remain open and freely available. This helps to promote the sharing and collaboration of software, as well as to prevent proprietary forks of the original software from being created. The details can be found here.