Introduction

The NOEL-V processor and the GRLIB IP library has support for Xilinx Artix-7 devices. This support consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contains a template designs for developments boards such as the  Arty A7: Artix-7 FPGA Development Board (A7-100T version) and infrastructure that automatically builds project files for Xilinx Vivado and synthesis tools such as Mentor Precision Hi-Rel and Synopsys Synplify Premier. More information about GRLIB and our IP cores is available on the SoC library page.

Example designs

We provide prebuilt bitstreams of the  Arty A7: Artix-7 FPGA Development Board NOEL-V template design. These bitstreams are intended for evaluation of software running on a NOEL-V SoC. To evaluate these designs, the following items are required:

•  Arty A7: Artix-7 FPGA Development Board (A7-100T version)
• Workstation with GNU/Linux or Microsoft Windows
• Xilinx software to program FPGA
• Bitstream, available further down on this page
• GRMON3 debug monitor - GRMON3 evaluation version (3.2.16 or later required)

The example design range is called NOEL-ARTYA7-EX:

• NOEL-ARTYA7 User's Manual
• NOEL-ARTYA7 Quick Start Guide
• NOEL-ARTYA7 FPGA configuration files
• NOEL-V documentation in the GRLIB IP Library User´s Manual

Software components and downloads for NOEL-ARTYA7:

• NOEL-V Software Overview
• NOEL-ARTYA7 DTS/DTB files (HW description needed by OS)