Section Processors - Category LEON CPU Family

LEON-PF

Introduction

The LEON5 processor and the GRLIB IP library has support for Microchip PolarFire FPGAs. This support consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contains a template designs for developments boards such as the PolarFire FPGA Splash Kit and infrastructure that automatically builds project files for Libero SoC and synthesis tools such as Mentor Precision Hi-Rel and Synopsys Synplify Premier. More information about GRLIB and our IP cores is available on the SoC library page.

LEON-PF board

Example designs

We provide prebuilt bitstreams of the PolarFire FPGA Splash Kit LEON5 template design. These bitstreams are intended for evaluation of software running on a LEON5 SoC. To evaluate these designs, the following items are required:

  • PolarFire FPGA Splash Kit (currently bitstreams are only available for the MPF300_ES device) 
  • Workstation with GNU/Linux or Microsoft Windows
  • Microchip software to program FPGA
  • Bitstream, available further down on this page
  • GRMON3 debug monitor - GRMON3 evaluation version (version 3.2.16 or later required)

The example design range is called LEON-PF-EX:

LEON-CERTUS/PRO

The LEON3 processor and the GRLIB IP library have support for Lattice/Frontgrade Certus/Pro-NX-RT FPGAs. This support consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contains template designs for development boards and a scripts infrastructure that automatically builds project files for Lattice Radiant and synthesis tools such as Synopsys Synplify. More information about GRLIB and our IP cores is available on the SoC library webpage.

We provide pre-built bitstreams of the LEON3 template design for the CertusPro-NX Versa Board and for the Certus-NX Versa Evaluation Board.

These bitstreams are intended for the evaluation of software running on a LEON3 SoC.

The bitstreams are just examples: the underlying SoC architecture can be extended and modified.

To evaluate these designs, the following items are required:

- Certus-NX Versa Evaluation Board or CertusPro-NX Versa Board

- Workstation with GNU/Linux or Microsoft Windows

- Lattice Radiant software to program the FPGA

- Bitstream, available further down on this page

- GRMON3 debug monitor (evaluation version), to connect to the LEON3 SoC and execute software

 

 LEON-CERTUS

- Board: Certus-NX Versa Evaluation Board

- LEON-CERTUS Quick Start guide

- LEON-CERTUS FPGA configuration files

 

 
 

 LEON-CERTUSPRO

- Board: CertusPro-NX Versa Board

- LEON-CERTUSPRO Quick Start guide

- LEON-CERTUSPRO FPGA configuration files

 

LEON-XCKU

Introduction

The LEON5 processor and the GRLIB IP library has support for Xilinx Kintex Ultrascale devices. This support consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contains a template designs for developments boards such as the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit and infrastructure that automatically builds project files for Xilinx Vivado and synthesis tools such as Mentor Precision Hi-Rel and Synopsys Synplify Premier. More information about GRLIB and our IP cores is available on the SoC library page.

Example designs

We provide prebuilt bitstreams of the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit LEON5 template design. These bitstreams are intended for evaluation of software running on a LEON5 SoC. To evaluate these designs, the following items are required:

The example design collection is called LEON-XCKU-EX:

LEON-V5QV

Introduction

The LEON processors and GRLIB IP library has support for the space-grade Xilinx Virtex-5QV FPGA. The Virtex-5QV support leverages the GRLIB Xilinx technology support that consists of a techmap layer that wraps specific technology elements such as memory macros and pads. GRLIB also contain template designs for a wide range of Xilinx development boards, including the Xilinx ML510 development board that is considered to be a good commercial option for prototyping V5QV designs. The GRLIB IP library infrastructure automatically builds project files for Xilinx ISE and synthesis tools such as Mentor Precision and Synopsys Synplify. More information about GRLIB and our IP cores is available on the SoC library page.

Example designs

The GRLIB IP library bitfiles package prebuilt includes bitstreams for development boards such as Xilinx ML510. The bitstreams can be used together with GRMON3 debug monitor - including the GRMON3 evaluation version.

LEON5 Processor

The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable and suitable for system-on-chip (SOC) designs.

LEON5 provides backward compatibility for most software implementations that have targeted LEON3 and LEON4 processors. The LEON5 primarily targets high-end FPGA:s and deep-submicron ASIC technologies. For legacy and less performant technologies, the LEON3 processor is the recommended choice that continues to be maintained.

  

Quick Links

- Documentation

- Development roadmap

- Detailed feature set

- DISCOURSE community (for open-source users)

  

 

- Software Ecosystem Overview

- Download open-source code (GPL license)

- Excel sheet for SOC area estimation

- GR765 - Octa-core LEON5FT SoC

Architecture

The processor pipeline design of the LEON5 is significantly enhanced compared to earlier LEON3 and LEON4 processors, and initial evaluations show that LEON5 can provide up to 85% faster execution for single-threaded integer benchmarks compared to LEON4. The main new feature of the LEON5 pipeline is the dual-issue functionality, allowing up to two instructions per cycle to be executed in parallel in the processor. To support the increased issue rate of the pipeline, the LEON5 has advanced branch prediction capabilities. The cache controller of the LEON5 supports a store buffer FIFO with one cycle per store sustained throughput, wide AHB slave support to enable fast stores and fast cache refill, as well as several other enhancements.

  

 

The LEON5 is interfaced using the AMBA 2.0 AHB bus (subsystem with Level-2 cache and AXI4 backend is also available) and supports the IP core plug&play method provided in the our IP library (GRLIB). The processor can be efficiently implemented on FPGA and ASIC technologies and uses standard synchronous memory cells for caches and register file. The processor supports the MUL and DIV instructions, an IEEE-754 floating-point unit (FPU) and Memory Management Unit (MMU). The cache system consists of separate I/D multi-set Level-1 (L1) caches with up to 4 ways per cache, and an optional Level-2 (L2) cache for increased performance in data intensive applications.

Fault Tolerance

The cache memories of the LEON5 processor are safeguarded from radiation-induced Single Event Upsets (SEUs) through a patent-protected error correction scheme. This scheme is capable of correcting single bit errors, detecting double bit errors, and even detecting 3-bit and 4-bit adjacent bit errors. The correction is implemented transparently in the cache controller without the need for software intervention or extra memory access. Additionally, the caches include a hardware mechanism that can be activated to automatically scrub the memories, preventing error accumulation.

  

 

The processor core can also be implemented in a dual-core lock step or a triple modular redundancy configuration (TMR). In this case, selected sub-blocks are instantiated multiple times (dual or triple redundant) with comparison logic and voters at the sub-block boundary.  See the IP User's Manual for detailed information.

 

Availability and licensing

LEON5 is part of the GRLIB IP library. The open-source version of the library is distributed under the GNU GPL license and can be downloaded here.

The LEON5  can also be obtained under commercial licensing conditions, enabling proprietary designs and taking advantage of a support agreement. Please see the GRLIB IP Core User's Manual - Processor license overview for the license types.

Contact us if you want to use LEON5 in a commercial product.

  

Evaluation bitfiles

We also provide LEON5 example bitfiles for evaluation purposes. FPGA programming files are available for the following FPGA boards:

- Microsemi PolarFire Splash Kit: LEON-PF example designs

- Xilinx KCU105: LEON-XCKU example designs

Synthesis

The LEON5 processor can be synthesized with common synthesis tools such as Xilinx Vivado, Synplify, and Synopsys DC. The processor model is highly portable between different implementation technologies.

Software Ecosystem

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON5 (kernels will need a LEON BSP). To simplify software development, We provide several toolchains and operating systems.

Check the software overview webpage for all the details.

Debugging is generally done using the GDB debugger, and a graphical front-end such as DDD or Eclipse. The GRMON monitor interfaces to the LEON5 on-chip debug support unit (DSU), implementing a large range of debug functions. The LEON5 processor will also be supported by our TSIM3 simulator.

  

Software compatibility

LEON5 provides backward compatibility for software designed for LEON3 and LEON4 systems with the following exceptions:

  • LEON5 does not support the SPARC V8e multiply-and-accumulate (MAC) instructions
  • LEON5 does not support the LEON-REX instruction set
  • Software that depend on version field values to identify LEON3 and LEON4 processors will see a different version value for LEON5

When HW virtualization is implemented and enabled, these incompatibilities can be hidden by the hypervisor.

Configurations

The LEON5 processor core is available as part of subsystems that also contain system peripherals. The subsystems can be used to select different processor configurations. The reference configurations listed below are the ones recommended by us since they are covered by regression tests. Software toolchains provided by us are developed and built considering the same configurations. It is possible to tailor additional configuration settings to create custom processor configurations by editing the VHDL generic (configuration parameter) assignments in the subsystem.

 

Configuration name LEON5-ADV
(tentative)		 LEON5-HP LEON5-GP LEON5-EP
(tentative)
Subsystem top-level leon5adv leon5sys leon5sys leon5ep
Required license Advanced General + GRFPU General + GRFPU Entry
Subsystem top-level generics (parameters)
perfcfg 0 0 1 2
fpuconf 1 1 1 0
Internal configuration
Issue rate Dual Dual Dual Single
I-cache 4x4KiB 4x4KiB 4x4KiB 1x4KiB
D-Cache 4x4KiB 4x4KiB 4x4KiB 1x4KiB
TLB I+D 24+24 24+24 16+16 4+4
FPU GRFPU5 GRFPU5*** GRFPU5*** NanoFPU
Bus Multi-AHB AHB AHB AHB
Bus data width 32 - 128* 32 - 128* 32 - 128* 32 - 128*
HW virt Yes No No No
L2 cache Yes (striped) Yes Yes No**
IOMMU Yes (striped) No** No** No**
Notes:
* Wide interface compatible also with 32-bit AHB masters and slaves
** L2 cache/IOMMU can be added externally as separate cores. These cores are licensed separately.
*** The higher performance GRFPU5 is recommended for configurations that need higher performance for floating-point calculations. GRFPU5 requires an additional license next to the Entry and General processor licenses.

 

Documentation

Item File
LEON5 IP core documentation

GRLIB IP Core User's Manual,  see LEON5SYS
LEON5 Product Brief

LEON5 Product Brief.pdf (November 2021)

 

Detailed Feature Set

The LEON5 processor has the following features:

  • SPARC V8 instruction set with V8e extensions and compare-and-swap
  • Advanced dual-issue pipeline
  • Complex dynamic branch predictor and small branch target buffer
  • Addition of Late ALU to decrease pipeline stalls
  • 64-bit single-clock load/store operation
  • 64-bit 4-port register file
  • Hardware multiply and divide units
  • Hardware floating-point support
  • Non-pipelined area efficient FPU (NanoFPU) or High-performance, fully pipelined IEEE-754 FPU including hardware support for denormalized numbers (GRFPU5)
  • High performance:
    • Dhrystone*: 3.23 DMIPS/MHz  (-O3, inlining allowed)
    • Coremark* : 4.52 CoreMark/MHz (-O3,-funroll-all-loops -finline-functions -finline-limit=1000)
      * All the results generated using BCC 2.0.7 toolchain

     

    		    
    • Separate instruction and data L1 cache (Harvard architecture) with snooping
    • Optional L2 cache: 256-bit internal, 1-4 ways, 16 Kbyte - 8 Mbyte
    • SPARC Reference MMU (SRMMU) with TLB
    • AMBA 2.0 AHB bus interface, 32-, 64- or 128-bit wide
    • Subsystem including processor and Level-2 cache with AXI4 backend also available
    • Advanced on-chip debug support with instruction and data trace buffer, and performance counter
    • Symmetric Multi-processor support (SMP)
    • Power-down mode and clock gating
    • Robust and fully synchronous single-edge clock design
    • Large range of software tools: compilers, kernels, simulators and debug monitors

     

    As with previous generation LEON processors, the LEON5 processor model is being continuously extended. Planned extensions include a more advanced version of LEON5 with virtualization features and higher-performance bus interconnect

     

    Development roadmap

    LEON5 is part of our GRLIB IP Library from version 2020.2. Pre-built bitstreams for FPGA development kits are also available.

    The table below shows milestones for the planned future extensions to the LEON5.

    Milestone Description Availability

    v3

     LEON5FT, support for tightly coupled memory, and internal memory scrubber.

    Available

    v4

    Release of LEON5 advanced subsystem (LEON5-ADV) with address-striped buses and IOMMU integration.

    Planned

    v5

    LEON5 virtualization extensions

    Planned

    v6

    LEON5 single-issue pipeline (LEON5-EP)

    Planned