Hardware Security Module

Hardware security module IP core with function to support crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.

Elliptic Curve Cryptography

The GRECC core implements encryption and decryption for an elliptic curve based on 233-bit key and point lengths. The implemented curve is denoted as sect233r1 or B-233.

AES 128

The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.

NOEL-3

Under development - More information coming soon!

DMA Controller with Crypto

GRDMAC2 is a flexible direct memory access controller with AHB or AXI4 interface. It can be configured to include hardware accelerators for AES-256 and SHA-256 functionalities.

DDR266

The DDRSPA can interface two 16,32 or 64-bit wide DDR266 banks. Both memory and configuration register accesses are performed through an AHB slave interface. The core also supports mobile DDR (LPDDR).

DDR2

The DDR2SPA can interface two 16,32 or 64-bit wide DDR2 banks. Both memory and configuration register accesses are performed through an AHB slave interface.‍

PC133 SDRAM

The FTSDCTRL interfaces PC133 SDRAM-compatible devices. Supported bus widths are 32-/39- and 64-bit. EDAC is only supported for 39-bit buses.

Combined PROM/IO/SRAM

The FTSRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code.

Combined PROM/IO/SRAM/SDRAM

The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code

NAND Flash

NANDFCTRL2 is a VHDL IP core implementing a NAND flash memory controller designed to operate with ONFI 4.0 devices and providing DMA transfers to and from the NAND flash memory.

SPI Memory Controller

SPIMCTRL maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. The core is highly configurable and supports most SPI Flash memory devices.

DDR2 / DDR3

FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.

CCSDS 121/123 Lossless Compression

The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 standards

FPGA Scrubber Controller

GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors. The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.

I²C Slave

I²C Master

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.

I²C to AHB Bridge

The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.

SPI to AHB Bridge

The SPI2AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.

SPI Controller

The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.

USB 2.0 Device Controller

The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.

USB 2.0 Host Controller

The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic.

USB Debug Link

The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus

Gbit Ethernet

The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

Ethernet 10/100

The GRETH is a 10/100 Mbit/s Ethernet MAC controller IP with AMBA host interface

CCSDS ECSS

The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the space sector. These IP cores implement functions commonly used in spacecraft data handling and management systems. Supporting Software Libraries and EGSE equipment are available.

CAN FD

GRCANFD is a CAN IP core implementing a CAN-FD controller compatible with both CAN 2.0 and CAN FD. GRCANFD features a DMA interface to fetch and store frames from/to external memory via AHB or AXI4 bus.

CAN 2.0B

GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.

MIL-STD-1553

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM).

PCI Bridge

The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems

SpaceWire CODEC

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).

SpaceWire node

The GRSPW2 core implements a SpaceWire link controller with SpaceWire RMAP support and AMBA host interface.

SpaceWire Router

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of FPGA and ASIC technologies.

SpaceFibre and WizardLink Interface

The GRHSSL IP Core is a versatile and highly configurable high-speed serial link controller written in VHDL, capable of implementing a SpaceFibre IP Core (GRSPFI), a WizardLink IP Core (GRWIZL), or both within a single solution.

LEON-CERTUS/PRO

Prebuilt bitstreams for the CertusPro-NX Versa Board and for the Certus-NX Versa Evaluation Board, intended for evaluation of software running on a LEON3 SoC.

LEON-XCKU

Prebuilt bitstreams of the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-V5QV

We provide prebuilt bitstreams of the Xilinx ML510 development board, considered to be a good commercial option for prototyping with the space-grade Xilinx Virtex-5QV FPGA. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC.

LEON-RTG4

Prebuilt bitstreams for the Microsemi RTG4 Development Kit. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC implemented in RTG4.

LEON3

The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments.

LEON4

The LEON4 processor builds on the success of its predecessors, providing enhanced performance and efficiency for demanding space and high-reliability applications.

LEON5

The LEON5 sets a new standard with exceptional processing and fault tolerance capabilities, perfect for advanced payloads and platform units in extreme environments.

NOEL-ARTYA7

Prebuilt bitstreams of the Arty A7 (Artix-7 FPGA Development Board). These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-XCKU

Prebuilt bitstreams of the AMD/Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-V

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.

GRLIB Xilinx

GRLIB Microchip

GRLIB NanoXplore

GRLIB Lattice

IEEE-754 Floating Point Unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The advanced design combines high throughput with low latency.

Fault Tolerant On-chip SRAM

L2 Cache

The L2C is a Level-2 cache IP core for processors with AHB interfaces. It is configurable to enable EDAC protection for the data and tag memory.

AHB Controller

APB Controller

AHB to AXI Bridges

Reed-Solomon

The Reed-Solomon IP cores provide an alternative to traditional Hamming codecs for memory protection - EDAC - functionality. The IP cores are especially useful in SDRAM and DDR memory controllers for space applications.

PPS Timer

GRPPSTIMER is a PPS timer IP core providing basic timekeeping functions such as an Elapsed Time counter, according to the CCSDS Unsegmented code specification. It also comprises a frequency synthesizer and can be synchronized using a Pulse Per Second (PPS) input signal.

Hardware Security Module

Hardware security module IP core with function to support crypto key storage, boot authentication, supervision, and offloading of cryptographic functions.

Elliptic Curve Cryptography

The GRECC core implements encryption and decryption for an elliptic curve based on 233-bit key and point lengths. The implemented curve is denoted as sect233r1 or B-233.

AES 128

The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.

NOEL-3

Under development - More information coming soon!

DMA Controller with Crypto

GRDMAC2 is a flexible direct memory access controller with AHB or AXI4 interface. It can be configured to include hardware accelerators for AES-256 and SHA-256 functionalities.

DDR266

The DDRSPA can interface two 16,32 or 64-bit wide DDR266 banks. Both memory and configuration register accesses are performed through an AHB slave interface. The core also supports mobile DDR (LPDDR).

DDR2

The DDR2SPA can interface two 16,32 or 64-bit wide DDR2 banks. Both memory and configuration register accesses are performed through an AHB slave interface.‍

PC133 SDRAM

The FTSDCTRL interfaces PC133 SDRAM-compatible devices. Supported bus widths are 32-/39- and 64-bit. EDAC is only supported for 39-bit buses.

Combined PROM/IO/SRAM

The FTSRCTRL uses a common 32-bit memory bus to interface 32-bit PROM, IO and SRAM devices. 8-bit PROM devices are also supported. It also provides EDAC correcting one and detecting two errors for the PROM and SRAM areas using a (39, 7) BCH code.

Combined PROM/IO/SRAM/SDRAM

The FTMCTRL can handle four types of devices: PROM, asynchronous static ram (SRAM), synchronous dynamic ram (SDRAM) and memory mapped I/O devices (I/O). The PROM, SRAM and SDRAM areas can be EDAC-protected using a (39, 7) BCH code

NAND Flash

NANDFCTRL2 is a VHDL IP core implementing a NAND flash memory controller designed to operate with ONFI 4.0 devices and providing DMA transfers to and from the NAND flash memory.

SPI Memory Controller

SPIMCTRL maps a memory device connected via the Serial Peripheral Interface (SPI) into AMBA AHB address space. The core is highly configurable and supports most SPI Flash memory devices.

DDR2 / DDR3

FTADDR is a memory controller for DDR2 and DDR3 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.

CCSDS 121/123 Lossless Compression

The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 standards

FPGA Scrubber Controller

GRSCRUB is an FPGA supervisor responsible for programming and scrubbing the FPGA configuration memory to prevent the accumulation of radiation-induced errors. The GRSCRUB IP currently supports the AMD/Xilinx Kintex UltraScale and Virtex-5 FPGA families.

I²C Slave

I²C Master

The I²C master core is a simple I²C master that provides a link between the I²C bus and the AMBA APB.

I²C to AHB Bridge

The I²C slave to AHB bridge core is a I²C slave that provides a link between the I²C bus and AMBA AHB.

SPI to AHB Bridge

The SPI2AHB bridge is an SPI slave that provides a link between a SPI bus (that consists of two data signals, one clock signal and one select signal) and AMBA AHB.

SPI Controller

The SPICTRL provides a link between the AMBA APB bus and the Serial Peripheral Interface (SPI) bus. Through registers mapped into APB address space the core can be configured to work either as a master or a slave.

USB 2.0 Device Controller

The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.

USB 2.0 Host Controller

The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic.

USB Debug Link

The Universal Serial Bus Debug Communication Link (USBDCL) provides an interface between an USB 2.0 bus and an AMBA-AHB bus

Gbit Ethernet

The GRETH_GBIT core implements a 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) with AMBA host interface. Receive and transmit data is autonomously transferred between the Ethernet MAC and the AMBA AHB bus using DMA transfers.

Ethernet 10/100

The GRETH is a 10/100 Mbit/s Ethernet MAC controller IP with AMBA host interface

CCSDS ECSS

The CCSDS/ECSS Spacecraft Data Handling IP cores represent a collection of cores that have been developed specifically for the space sector. These IP cores implement functions commonly used in spacecraft data handling and management systems. Supporting Software Libraries and EGSE equipment are available.

CAN FD

GRCANFD is a CAN IP core implementing a CAN-FD controller compatible with both CAN 2.0 and CAN FD. GRCANFD features a DMA interface to fetch and store frames from/to external memory via AHB or AXI4 bus.

CAN 2.0B

GRCAN is a CAN 2.0 IP core that implements an internal CAN controller and an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages via the DMA engine.

MIL-STD-1553

The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus Monitor (BM).

PCI Bridge

The GRPCI2 IP core provides a 32-bit master/target interface for AMBA AHB-2.0 systems

SpaceWire CODEC

The GRSPW_CODEC core implements a SpaceWire encoder-decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C).

SpaceWire node

The GRSPW2 core implements a SpaceWire link controller with SpaceWire RMAP support and AMBA host interface.

SpaceWire Router

The GRSPWROUTER IP core is a VHDL model of a SpaceWire routing switch as defined in the ECSS-E-ST-50-12C standard. The core is highly configurable, flexible and portable to a wide variety of FPGA and ASIC technologies.

SpaceFibre and WizardLink Interface

The GRHSSL IP Core is a versatile and highly configurable high-speed serial link controller written in VHDL, capable of implementing a SpaceFibre IP Core (GRSPFI), a WizardLink IP Core (GRWIZL), or both within a single solution.

LEON-CERTUS/PRO

Prebuilt bitstreams for the CertusPro-NX Versa Board and for the Certus-NX Versa Evaluation Board, intended for evaluation of software running on a LEON3 SoC.

LEON-XCKU

Prebuilt bitstreams of the Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a LEON5 SoC.

LEON-V5QV

We provide prebuilt bitstreams of the Xilinx ML510 development board, considered to be a good commercial option for prototyping with the space-grade Xilinx Virtex-5QV FPGA. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC.

LEON-RTG4

Prebuilt bitstreams for the Microsemi RTG4 Development Kit. These bitstreams are intended for evaluation of software running on a LEON3 or LEON4 SoC implemented in RTG4.

LEON3

The LEON3 processor offers robust fault tolerance and performance for space and high-reliability applications, including satellites and scientific instruments.

LEON4

The LEON4 processor builds on the success of its predecessors, providing enhanced performance and efficiency for demanding space and high-reliability applications.

LEON5

The LEON5 sets a new standard with exceptional processing and fault tolerance capabilities, perfect for advanced payloads and platform units in extreme environments.

NOEL-ARTYA7

Prebuilt bitstreams of the Arty A7 (Artix-7 FPGA Development Board). These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-XCKU

Prebuilt bitstreams of the AMD/Xilinx Kintex UltraScale FPGA KCU105 Evaluation Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-PF

Prebuilt bitstreams of the Microchip PolarFire FPGA Splash Kit. These bitstreams are intended for evaluation of software running on a NOEL-V RISC-V SoC.

NOEL-V

The NOEL-V is a synthesizable VHDL model of a processor that implements the RISC-V architecture. The NOEL-V can be implemented as a dual-issue processor, allowing up to two instructions per cycle to be executed in parallel.

GRLIB Xilinx

GRLIB Microchip

GRLIB NanoXplore

GRLIB Lattice

IEEE-754 Floating Point Unit

The GRFPU is an IEEE-754 compliant floating-point unit, supporting both single and double precision operands. The advanced design combines high throughput with low latency.

Fault Tolerant On-chip SRAM

L2 Cache

The L2C is a Level-2 cache IP core for processors with AHB interfaces. It is configurable to enable EDAC protection for the data and tag memory.

AHB Controller

APB Controller

AHB to AXI Bridges

Reed-Solomon

The Reed-Solomon IP cores provide an alternative to traditional Hamming codecs for memory protection - EDAC - functionality. The IP cores are especially useful in SDRAM and DDR memory controllers for space applications.

PPS Timer

GRPPSTIMER is a PPS timer IP core providing basic timekeeping functions such as an Elapsed Time counter, according to the CCSDS Unsegmented code specification. It also comprises a frequency synthesizer and can be synchronized using a Pulse Per Second (PPS) input signal.

BCC2 - LEON bare-metal cross-compiler system

NOEL Bare-Metal Cross-compiler System (NCC)

NCC is a bare-metal toolchain for NOEL-V. It can be used for developing single-threaded C and C++ applications.

VxWorks 7

VxWorks 7 delivers advanced features and a flexible development environment for the LEON processors, ensuring robust performance and compatibility with various development hosts. We also provide VxWorks 7 SR0650 board support packages for NOEL processors.

VxWorks 6.9

VxWorks 6.9 provides a stable, mature platform with extensive driver support, ideal for legacy systems.

Linux for LEON

Linux kernel. All host tools and Linux software are provided in full source.

Zephyr

Zephyr RTOS provides a lightweight, efficient real-time operating system environment with a small footprint, making it ideal for embedded systems requiring minimal resource usage.

GRBOOT

GRBOOT is a flight system software suite targeting GR740, GR712RC and UT700 systems. The purpose of GRBOOT is to provide initialization, self-test and application loading functionality to payload and onboard computers.

GRBOOT-STANDBY

GRBOOT-STANDBY is a SpaceWire/PUS standby extension for the GRBOOT flight boot loader. The software is compatible with the standby function as described in SAVOIR-GS-002.

GR712RC Boot Software

GR712RC Boot SW is a flight system software suite targeting GR712RC systems. The purpose of GR712RC Boot SW is to provide initialization, maintenance, and application loading functionality to a payload or on-board computers.

MKPROM2

MKPROM2 is a utility program that converts a LEON RAM application image into a bootable ROM image. The resulting bootable ROM image contains the system initialization code, an application loader, and the RAM application itself. The RAM application is compressed with a modified LZSS algorithm, typically achieving a compression factor of 2.

TM/TC Software Stack API

Implements a Software Stack for receiving and transmitting TM/TC using the CCSDS/ECSS hardware IPs for RTEMS, VxWorks and Linux in LEON environment.

RTEMS-5 File System backend

Software package implementing the backend to the file system layers of RTEMS-5 for certain NOR FLASH memory components.

RTEMS Cross-compiler System (RCC)

RCC provides a real-time operating system environment with comprehensive support for device drivers, making it suitable for time-critical applications requiring reliable performance and extensive hardware support.

RTEMS5 for RISC-V NOEL

The software provided are mainly RISC-V NOEL BSPs, device drivers and compiler toolchains together with the integration into the developer tools/ecosystem

Linux for RISC-V NOEL

BCC1 - LEON bare-metal cross-compiler system

Bare-C Cross-Compiler System for LEON3/4 GCC 3.4.4 and GCC 4.4.2

Gaisler Buildroot

Gaisler Buildroot distribution, aimed for both LEON and NOEL, based on LTS versions of the open-source Buildroot tool, is our officially supported Linux development and build environment.